1. Field of the Invention
The present invention generally relates to semiconductor memory, in particular, to a structure of memory cell with asymmetric cell structure and method for fabricating the memory cell.
2. Description of Related Art
The flash memory cell can be formed by two stacked gate structures on a substrate, also known as 2T memory cell, to improve performance, in which each gate structure is stacked by a lower gate and an upper gate. One of the two gate structures server as a selection gate, in which only the lower gate is applied with a selection voltage to select this cell and the upper gate is not used. Another one of the two gate structures is used to store the binary data, in which the lower gate is a floating gate for storing data and the upper gay is applied with a control voltage to perform reading operation, writing operation and erasing operation.
However, the conventional structure for the memory cell with two gate structures may get worse in performance after a certain number of operations. In other words, the life time is not long enough.
How to design a memory cell with better performance is still under developing in the art.